1. Field of the Invention
The invention relates to amplifiers, and more particularly to amplifiers for amplifying voltages of electrical signals.
2. Description of Related Art
Amplifiers are widely used in electrical circuits such as, for example, memory circuits. FIG. 1 illustrates a memory circuit including a sense amplifier 110 which amplifies memory signals. The memory includes an N-column array of memory cells 120.i,j. Only one row of the array is shown for simplicity. Each memory cell 120.i,j has two states. One state is interpreted as a logic 1, and the other state is interpreted as a logic 0.
Each memory cell of each column j=1, . . . , N is connected to two complementary bit lines BL.j, BL.j. To read a memory cell 120.i0,j0 in a row i0 and a column j0, a row decoder (not shown) enables all the memory cells 120.i0,j of row i0 to provide their states on the respective bit lines BL.j, BL.j. In one of its two states, the memory cell 120.i0,j provides a high voltage on bit line BL.j and a low voltage on bit line BL.j. In the other state, the memory cell provides a low voltage on bit line BL.j and a high voltage on bit line BL.j.
Y-pass gate 130 receives the column address j0 on column address lines 132 and selects the column j0 by putting out a high voltage signal on the line 140.j0 while keeping the other lines 140.j low. Consequently, NMOS pass transistors 150.j0,1, 150.j0,2 turn on, and all the other pass transistors 150.j,1, 150.j,2 turn off. Hence, bit lines BL.j0 BL.j0 become connected to respective lines 160, 162 which are connected to respective inputs D, D of sense amplifier 110. Sense amplifier 110 produces on its output OUT a voltage indicative of whether the voltage on input D is higher or lower than the voltage on input D.
The reading speed and the power efficiency of the memory of FIG. 1 suffer from the high capacitance of lines 160, 162. Line 160 has a high capacitance because line 160 is connected to the sources of all the N pass transistors 150.i,1, i=1, . . . , N. Line 162 has a high capacitance for a similar reason. Because of the high capacitance, charging the lines 160, 162 to proper voltages takes a long time and requires much power.
An improved memory with reduced capacitance is illustrated in FIGS. 2A, 2B and 2C. Here the N memory array columns are grouped in groups of eight columns. Y-pass gate 210 selects one column from each group in response to the column address signals on lines 212. Y-pass gate 210 has eight output lines 140.1 through 140.8. Line 140.1 is connected to the gates of the pass transistors of the first column of each group, that is, to the gates of pass transistors 150.1,1, 150.1,2, 150.9,1, 150.9,2, and so on. Line 140.2 is connected to the gates of the pass transistors of the second columns of each group, and so on. Each group k has line 160.k connected to the sources of the pass transistors 150.i,1 of the group, and each group k has line 162.k connected to the sources of the pass transistors 150.i,2 of the group. Each group k has its own first sense amplifier 220.k whose inputs D1, D1 are connected, respectively, to lines 160.k, 162.k. Each first sense amplifier 220.k has also a select input S. Y-pass gate 230 receives a column address on lines 234 and produces the signals for the select inputs S so as to select only one first sense amplifier 220.k. The selected first sense amplifier 220.k amplifies the voltage difference on its inputs D1, D1 and produces the corresponding amplified voltages on its output OUT1, OUT1 All the outputs OUT1 are connected to node SA which is connected to input D2 of a second sense amplifier 240. All the outputs OUT1 are connected to node SA which is connected to input D2 of second sense amplifier 240. Second sense amplifier 240 amplifies the voltage difference on the nodes SA, SA and produces an output voltage on its output OUT2 connected to the memory output OUT.
The memory of FIGS. 2A, 2B and 2C is faster because the capacitance of lines 160.k, 162.k connected to the selected first sense amplifier 220.k plus the capacitance of nodes SA, SA is lower than the capacitance of lines 160, 162 of FIG. 1. Indeed, each of lines 160.k, 162.k is connected to only eight bit lines (through pass transistors), and each of nodes SA, SA is connected to only N/8 respective outputs OUT1 or OUT1, while each of lines 160, 162 of the memory of FIG. 1 is connected to N bit lines.
However, the capacitance of nodes SA, SA is fairly high, and this capacitance limits the memory speed and increases the memory power consumption.
In order to increase the memory speed, nodes SA, SA are resistively shorted to each other by an equalizing transistor 250 whose gate is connected to a reference voltage (not shown). Transistor 250 reduces the voltage difference on nodes SA, SA and hence reduces the time and the power required for the voltage difference to switch states.
There is a need, however, for even faster and more power efficient amplifiers for memories and for other circuits.
Another challenge in an amplifier design is adjusting the amplifier for different power supply voltages, for example, adjusting the amplifier when the power supply voltage VCC is changed from 5.0V such as used in larger computers to 3.0V such as used in laptop, notebook, and sub-notebook computers. This challenge is illustrated by FIG. 3 which is a circuit diagram of a prior art amplifier circuit 304 used in each first sense amplifiers 220.k and in second sense amplifier 240. Inputs D, D of FIG. 3 correspond to inputs D1, D1 of each first sense amplifier 220.k and to inputs D2, D2 of second sense amplifier 240. Output OUT correspond to output OUT1 of each first sense amplifier 220.k and to output OUT2 of second sense amplifier 240. A similar circuit (not shown) provides output OUT1 of each first sense amplifiers 220.k. When circuit 304 is used for second sense amplifier 240, output OUT of circuit 304 is used for output OUT2 of sense amplifier 240, and output OUT1 of circuit 304 is unused.
Matched PMOS transistors 310, 314 of circuit 304 form a current mirror and source equal currents to the drains of respective transistors 320, 324. Matched NMOS transistors 320, 324 whose gates are connected to, respectively, inputs D, D, sink current through NMOS transistor 330 whose gate is connected to input S and whose source is connected to ground. Transistors 320, 324 must stay in saturation in order to provide fast voltage switching on output OUT in response to voltage changes on inputs D, D. The saturation condition requires that the VDS voltages (drain-to-source voltages) of these transistors stay above a certain minimum value VDSSAT. However, when VCC decreases to 3.0 V, VDS of each transistor 320, 324 decreases and may fall below VDSSAT. Further, the current through transistor 330 decreases making the amplifier circuit 304 slower. Hence, circuit 304 needs to be changed for fast operation at a lower VCC value such as 3.0 V. It is desirable to provide an amplifier which is simple to adjust to a lower VCC value.